The serial peripheral interface (SPI) is a synchronous serial interface providing full-duplex communication between two or more devices. One device becomes configured as a master and another is configured as a slave. The master initiates transfers in communication with a slave, controls a serial clock provided to all slaves and provides a chip select signal to access a targeted slave. A typical slave may be a peripheral device in a system, such as a printer, a sensor, a display driver, or a memory device.
Typically, the interface between serial peripheral interface devices is configured with four wires and their associated signals. A serial clock (SCLK) signal is controlled by the master and distributed to all slave devices in the system. A slave select (SS) signal, or alternatively, a chip select (CS) signal, is also provided to all slave devices. In a first alternative configuration, all devices are connected in series in a cascaded connection. In this situation, a single chip select signal is provided in parallel to all cascaded slaves. With an output of a given slave device connected to the input of a subsequent slave device in the cascade configuration, the single chip select and the appropriate number of clocks allows all slave devices to operate as one large capacity device. This alternative keeps to a minimum the amount of logic required in the master for determining a targeted slave.
In a second alternative configuration, a master selects one of many slaves for communication. The master contains appropriate logic to determine a single one of the many slaves for selection and asserts a single chip select signal for the targeted slave. A chip select line is provided from the master to each of the slave devices to effect the access of a single one of the slaves according to the additional selection logic.
The third and fourth wires of the interface carry serial data to and from master and slave. Data is carried from master to slave by the Master-Out-Slave-In (MOSI) wire. Alternatively, data from the slave to the master is provided by the Master-In-Slave-Out (MISO) wire from each slave that communicates with the master.
A benefit of a serial communication interface is that wiring is simpler due to data being transferred over a single wire in each direction instead of there being a wire for each bit of data. An additional benefit is that the simpler wiring reduces electrical cross-talk effects. The reduction in cross-talk allows an additional benefit in that connections are typically able to span a greater distance since signal quality is not degraded by the cross-talk effects encountered in configurations wired in parallel.
Increasing performance requirements in serial buses means that both memory read and non-memory read commands need be decoded and responded to within ever decreasing cycle times. As memory read access times have steadily decreased, a corresponding decrease in non-memory read times has been both a requirement and a challenge. Performance increases of internal memory and a corresponding reduction in read-cycle times of memory arrays has created an a critical requirement for producing results for a non-memory read-cycle time in order to prevent non-memory read commands from becoming a critical limitation of system performance. What is needed it is a way to determine a potential non-memory read command as early as possible in order to prepare a response to the non-memory class of command as quickly as is possible for the memory reads of the same system.